Gate notching is one technique to increase transistor speed by reducing the gate length and the source drain overlay capacitance. The challenges for this technology are repeatability and measurability as well as the difficulties associated with the spacer and implant integration (slide 1).
In the traditional silicon gate etch approach, the profile is formed with a sidewall passivation layer extending over the entire height of the profile. For the formation of a notched gate, the passivating silicon etch step is stopped at a desired height (notch height). This can be accomplished for instance with predictive endpoint. The bottom of the profile is etch with a fluorine containing etch chemistry which prevents to a large extend the formation of a protective sidewall layer. An HBr, Cl2, O2 and N2 containing overetch or notch step is introduced to etch laterally into the profile to form the desired notch. The notch depth and hence the gate length depends on the etch time which makes gate length control very dependent on the reactor condition (slide 2).
Slide 3 illustrates that germanium containing gate stacks are very well suited for the formation of notched gates. The notch height is controlled by the thickness of the germanium containing layer.
XPS spectra of the silicon gate sidewall show that traditional HBr / Cl2 / O2 based etch chemistries form dense and thick silicon oxide passivation layers, while Cl2/SF6 forms an anisotropic profile without any passivation layer thanks to a fast etching rate and a slow spontaneous etching rate of Cl species (slide 4).
The built up of silicon oxide containing layers on the reactor wall can severely impact the reproducibility of the lateral etch rate during the notching step (slide 5).
Slide 6 compares SF6 and CF4 containing etch processes. While Cl2/SF6 process chemistries form a passivation free sidewall layer, a mixture of Cl2 and CF4 is not suited for the notching due to the formation of a thin, probably carbon containing passivation layer.
Slide 7 shows the impact of aspect ratio dependent etching (ARDE) on the gate length of dense and isolated lines limits the application of the notched gate process to gate structures with a width larger than 100 nm. Below 100 nm, the critical dimensions of dense and isolated lines start to deviate significantly.
Slide 8 summarizes the key features of the notched gate process.
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