Saturday, February 3, 2007

Materials and Gas Systems in Plasma Etching

Slide 1: General Overview of materials and gas systems relevant for VLSI production

Slide 2: Plasma Etch Chemistries for Materials Systems with Giant (GMR) and Colossal (CMR) Magneto Resistance: NiFe

Slide 3: Plasma Etch Chemistries for Materials Systems with Giant (GMR) and Colossal (CMR) Magneto Resistance: NiMnSb

Slide 4: Plasma Etch Chemistries for Materials Systems with Giant (GMR) and Colossal (CMR) Magneto Resistance: CMR materials

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Non-equilibrium Plasmas

Plasmas used in plasma processing are non-equilibrium plasmas. Non-equilibrium plasmas are characterized by charged species with a much higher kinetic energy than neutral species (slide 1).

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Reactive and Condensable Species

Neutral species that arrive at the wafer surface can stick to the surface and react. Depending on the sticking coefficients and reaction probabilities, reactive and condensable species can be distinguished among the species in the feed gas and the reaction products (slide 1). The balance between reaction and condensation influences the etch profile.

Reactive species: React chemically with surfaces. Reactions are not very temperature sensitive because of low activation energies for the reactions. Surface coverage is typically saturated at a few monolayers.

Condensable species: Form liquid or solid films on surfaces. Surface coverage dependents strongly on the substrate temperature.

Slide 2 shows reactive and condensable species for the example of tungsten Etching with Cl2/O2.

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Electron Energy Distribution Function (EEDF)

The electron temperature of the plasma is generally lower than the threshold energies for dissociation of the feed gas molecules. Dissociation and ionization are induced by the high energy tail of the EEDF (slide 1). The EEDF for inductive and capacitive plasmas are different.

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Electron - Molecule Collisions

Electron Molecule Collisions are the main channel for the creation of species that are used in plasma etching: ions and radicals. Three fundamental reactions can occur when an ion strikes a molecule: electron attachment, ionization and dissociation (slide 1).

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Electron Reactions in Plasmas

Electron Impact Reactions (slide 1) convert relatively inert molecules into very reactive radicals. The role of reactive radicals is very important in plasma etching: most of the plasma surface chemistry is achieved thanks to radicals. The role of radicals depends also on the plasma density: in low density RIE discharges, they play a fundamental role whereas ions may be strongly involved in the chemistry in high density plasmas.

Electron Impact Ionizations (slide 2) transform atoms and molecules into ions. Dissociation and ionization may often simultaneously occur: this process is called Dissociative Ionization.

Some molecules tend to capture low energy electrons and form negative ions. This process is called Electron Attachment (slide 3). It produces negative ion fragments as well as neutrals and leads to lower plasma densities. The energy acquired by the molecule in the capture process can cause the molecule to dissociate. This process is called Dissociative Electron Attachment.

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Surface Processes in Plasma Etching

Physical and chemical surface processes are central to plasma processing. Reactive species are created in the discharge and transported to the surface where they can react and desorp. The reaction and desorption is frequently assisted by the energy of impacting ions. Slide 1 describes these processes for the etching of silicon in fluorine based plasmas.

Besides the reaction at the surface, the discharge equilibrium itself affected by surface processes such as positive ion neutralization and secondary electron emission at surfaces. In processing discharges (ion energy between 10-1000 eV), all positive ions are immediately neutralized at the surface (slide 2).

Heavy particles (ions and neutrals) exhibit the same behavior when they impact surfaces:
- at low thermal energies: physi-and chemisorption and desorption can occur.
- in the tens of electronvolts energy range: molecules can fragment into atoms.
- in the hundreds of electronvolts range: atoms can be sputtered from the surface.
- in the thousands of electronvolts range: implantation is important.

Adsorption and desorption are very important for plasma processing since one or the other of these reactions is the rate limiting step for a surface process (slide 3).

Adsorption A + S -> A:S is the reaction of a molecule with a surface, desorption is the reverse reaction.
Physisorption: Weak attractive van der Waals force between a molecule and a surface. Physisorption is exothermic with Ephys ~ 0.01-0.25 eV. Physisorped molecules are so weakly bound to the surface that they can diffuse rapidly along the surface.
Chemisorption is the formation of a chemical bond with the atom or molecule and the surface. The reaction is strongly exothermic, Echem ~ 0.4-4 eV.

Fragmentation: Ionic and neutral molecules with enough impact energy can fragment into atoms that are reflected or adsorbed when they hit a surface (slide 4). The threshold in energy is of the order of the molecular bond (at energies four or five times above the threshold, 50% of the molecules fragment). High energy molecular ions (energy higher than 50 eV) often fragment when they hit surfaces. Large molecules show frequently delayed fragmentation. The kinetic energy of the impact is transferred into internal energy and redistributed among the bonds as vibrational and rotational energy. If this internal energy is higher than the bonding energy, the ion fragments along this bond. Large molecules with only one type of atoms like C60 are especially resilient to collision induced fragmentation.

Sputtering: At energies above 20-30 V, heavy particles can sputter atoms from a surface. The sputtering yield increases rapidly with energy up to a few hundred volts generating collision cascades in the solid bombarded. Above these energies, the yield is independent of the projectile energy and the target atom density.

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Ions and Radicals in Plasmas

The energy that is transferred to a plasma is ultimately stored in high energy plasma particles such as fast electrons, photons as well as atoms in high energy states: ions and radicals (slide 1).

Positive and negative ions co-exist in plasmas. Positive ions are very important since they are accelerated through the sheath. Negative ions play an important but secondary role since they don’t reach the wafer under normal conditions. They can influence plasma properties but rarely participate in the surface reactions of the etch process. When electronegative gases are used in plasma etching, the density of negative ions in the plasma can be higher than the electron density. In processing plasmas, the ion to neutral fraction ranges from 10-2 for high density plasmas to the 10-4 to 10-6 range for conventional RIE plasmas.

Radicals are more abundant than ions in molecular gas glow discharges because they are generated at a higher rate than ions (lower threshold energy and ionization is often dissociative) and they survive longer in the discharge than ions.

Slide 2 shows typical relative concentrations of plasma species in low density plasmas (Magnetically Enhanced Reactive Ion Etching (MERIE) and Single Frequency Capacitively Coupled Plasmas (SF-CCP)) and in high density plasmas (Inductively Coupled Plasmas (ICP), Ultra High Frequency Capacitively Coupled Plasmas (UHF-CCP), Double Frequency Capacitively Coupled Plasmas (DF-CCP) and Electron Cyclotron Resonance (ECR) Plasmas).

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Plasma Etch Mechanisms

Plasma etching is a complex process involving several elementary processes or mechanisms. Some of these processes are illustrated on slide 1:
- chemical etching
- ion induced or enhanced etching
- physical etching / ion bombardment
- trenching
- sidewall passivation
- mask erosion

Anisotropic plasma etching has two major components (slide 2), chemical etching (neutrals and radicals of the plasma) and physical bombardment (ion assisted etching reactions). VLSI plasma etch processes are characterized by a varying significance of the chemical and physical components. Aluminum etching is a very chemical etch while SiO2 etching has a very strong physical component. Silicon etching has a strong chemical and physical components. To understand plasma etching mechanisms and improve processes, it is essential to describe these two components and the synergy existing between these two components.

The synergy between the chemical and physical components in plasma etching was first shown in an experiment by Coburn and Winters. In this classical experiment, the silicon etch rate increased by one order of magnitude when XeF2 was present at the surface and the argon ion beam was turned on (slide 3).

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Spontaneous Reactions in Plasma Etching

Chemical or so-called “spontaneous” etching is the result of the interaction of reactive free radicals with the surface. Free radicals are electrically neutral species that have incomplete outer shells such as CF3 and F.

The mechanism of chemical etching consists of three elementary steps:
- adsorption of reactive species on the surface and dissociation if it is a molecule
- etch products formation (chemical reaction)
- etch products desorption

In a spontaneous etch process, these steps proceed without the need for activation by ion bombardment. Examples for spontaneous etch reactions are given in slide 1.

A classical example of a chemical reaction which is relevant for plasma etching is the reaction of XeF2 with silicon. Coburn and Winters studied this system and could provide experimental evidence that Ar bombardment enhances the etch rate in this system. This was the proof for the concept of ion enhanced chemical etching which is the foundation of plasma etching. The etch mechanism of XeF2 is actually quite complex and very dependent on the surface temperature as shown on slide 2.

Another way to generate free fluorine without inhibitors is to mix CF4 and O2 in the appropriate ratio (slide 3). The etch rate in the experiment by Mogab, Adams and Flamm peaked for an O2 percentage of 10 to 20 % in the gas feed.

Slide 4 describes etch rate effects for etching silicon in a SF6 plasma. The silicon etch rate is driven by radical concentration in the gas phase. A higher source power leads to deeper SF6 dissociation and more free fluorine. A higher SF6 flow reduces the concentration of reaction products in the gas phase. For very high source power / SF6 flow combinations, the etch rate saturates, indicating that surface processes are becoming rate limiting.

Slide 5 illustrates the importance of the chemical aspect of plasma etching on etch rate selectivities. The silicon to nitride selectivity for a SF6 plasma is shown as a function of Vdc. The lower Vdc, the more chemical the etch. The results show that nitride requires ion bombardment to be etched in a fluorine based plasma while silicon etches spontaneously. Therefore very high selectivities can be obtained by reducing the ion component of the etch. Decoupled ICP or ECR plasma sources and downstream reactors are suited for this application.

The most significant application of chemical etch processes in advanced logic device manufacturing is the so called resist trim process (slide 6). In-situ XPS studies show the presence of a perturbed layer on the sidewall of the resist. It’s thickness depends on the bias power, i.e. ion energy. The thickness of the layer also depends on the microloading conditions, i.e. is different for dense and isolated features. The trim rate slows down for thicker perturbed layers. Bias power, among others, can be used to adjust the dense/iso effect of the trim process.

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The Role of Ion Bombardment in Plasma Etching

When a surface is exposed to ion bombardment, atoms and molecules can be ejected. This is called Sputtering (slide 1).
Physical sputtering is a non selective phenomenon (materials of different nature can be sputtered at similar rates). It is also a directional phenomenon which helps in obtaining anisotropic etching profiles.
Ion induced damage and mixing: Ion bombardment may favor neutral dissociation at the surface and increase the number of adsorption sites by generating some surface roughness and generating dangling bonds.
Ion enhanced chemical reaction: Ion bombardment may favor the formation of etch products.
Chemical sputtering: Ion bombardment may favor the desorption of etch by products.
Ions as a source of reactants: Ions get neutralized when they reach the surface, they become an additional source of reactive species.

The synergy between ion bombardment and chemical etching was first shown by Coburn and Winters in the classical experiment shown on slide 2.

Besides enhancing the chemical etch, ions also play a major role in removing non-volatile by-products or etch products that require an activation energy to desorp from the surface. The removal of by-products and their re-deposition onto the feature sidewall is the fundamental reason why plasma etching can obtain anisotropic profiles (slide 3)

Factors that influence the anisotropy are (slide 4):
Ion energy flux (ion density and ion energy): Primarily responsible for the etch anisotropy in plasma etching. In general an increase in ion energy flux leads to a better anisotropy.
Neutral to ion flux ratio: The lower the neutral to ion flux ration the better the anisotropy.
Natural species reactivity: Probability for spontaneous reaction of neutral species to react with the surface.
Deposition rate for non-volatile etch products forming a passivation layers at the feature sidewalls.
Substrate temperature: Influences neutral species reactivity and reaction product deposition.

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Etching Profiles

In most cases, the desired etch profile is square shaped (slide 1). To obtain this perfect profile, etch and passivation have to be carefully balanced and if need readjusted as the aspect ratio of the structure increase. Excessive sidewall passivation leads to tapered profiles which are desired for shallow trench isolation etch. The lack of sidewall passivation and excessive spontaneous chemical etching leads to undercutting. Ion deflection in very narrow spaces can lead to bowing. At the interfaces of layers such as the interface between the gate oxide and the poly-Si layer, notching has to be avoided.

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Trenching

Profile trenching is caused by ion bombardment (slide 1). Ions arriving at grazing angles on the feature sidewalls get reflected and accumulate leading to a localized higher etch rate. This effect is well known in sputter etching and in plasma processing. At least two possible explanations for trenching can be found in the literature:
- Ion scattering from sloped sidewall surfaces (S. Van Nguyen, D. Dobuzinski, S.R. Stiffler, G. Chrisman; J. Electrochem. Soc. 138 (1991) 1112 / T.J. Dalton, J.C. Arnold, H.H. Sawin, D. Corliss; J. Electrochem. Soc. 140 (1993) 2395 / J.C. Arnold, H.H. Sawin; J. Appl. Phys. 70 (1991) 5314 and others)
- Ion deflection due to differential charging of microstructures (G.S. Hwang, K.P. Giapis; Appl. Phys. Lett. 71 (1997) 458 / M. Schaepkens, G.S. Oehrlein; Appl. Phys. Lett. 72 (1998) 1294 and others).

Slide 2 illustrates research results on the role of the plasma chemistry on trenching. Severe trenching is observed with pure chlorine chemistry in a bias power range of less than 100 W, while HBr and HCl show little or no trenching. This could be explained by the angular distribution of the impacting ions or the presence of fast protons neutralises the negative charging of the mask in the case of HBr and HCl.

Bogart et al. showed that the microtrench shape and depth seems to be in a first approximation independent on the nature of the mask (oxide vs. resist). Hence charging does not seem to be the primary cause of microtrench formation. They concluded that the angular distribution of ions impacting and subsequently scattering from the etching feature are likely to be the primary cause of non-vertical sidewall and microtrench formation (slide 3).

Schaepens and Oehrlein found microtrenching to be influenced by the direction of a weak magnetic field. This field changes only the angular distribution of the electrons. The ions are too immobile. This result strongly supports the differential charging mechanism (slide 4).

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Sidewall Passivation

At room temperature etch anisotropy is always obtained thanks to the formation of a sidewall passivation layer: The sidewall passivation layer can be formed by different mechanisms (slide 1):
- Mask etch products sputtered into the plasma gas phase by energetic ion bombardment and get re-deposited on the feature sidewalls.
- Condensation of some molecules or atoms originating from the dissociation of the feed gas stock.
- Etch by products dissociation in the gas phase leading to the formation of partially volatile or non volatile etch by products which get re-deposited on the feature sidewalls.
- Direct line of sight deposition of non volatile etch by -products.

Slide 2 illustrates the various passivation mechanisms.

Different etch processes are dominated by different passivation mechanisms (slide 3). This has extremely important consequences for the response of process results like CD, profile angle and profile microloading to process parameters like pressure, source and bias power. Aluminum etch is dominated by re-deposition of resist etch products on the Al sidewalls generating a carbon-based passivation layer. In dielectric etch, condensation of CFx species from the fluorocarbon gas on the oxide sidewalls and re-deposition of resist etch products both contribute to the CFy passivation layer formation. Re-deposition of silicon etch products from the plasma gas phase and direct line of sight deposition of silicon etch products drive the passivation layer formation during silicon (gate) etch.

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Loading Effects and Aspect Ratio Dependent Etching

Loading effects in plasma etching can be classified into macroscopic loading, microscopic loading and etch rate dependent etching, ARDE (slide 1).

Macroscopic loading causes an Etch rate decreases when the total area of the material to be etched decreases. The effect is caused by the consumption of reactive species during the etch process.

In addition, identical features are etched with different rates depending on their position with respect to open area features (dense areas, semi dense areas, open areas). This effect is called microloading.

ARDE is an effect where features with a high aspect ration (depth/width) have a higher etch rate then those with a small aspect ratio. Under certain conditions this effect can be reversed and is then called reverse ARDE.

Macroscopic loading (slide 2) is most common for isotropic etches with spontaneous etch mechanism, for instance removal of poly-Si with SF6 based plasmas. Certain silicon gate overetch processes also show significant macroloading. Macroloading is related to a change in plasma composition when wafers with different open areas are being etched, i.e. a change in the loading of the plasma with reactants and reaction products. Simply increasing the concentration of reactive species by increasing the source power is not practical because of the simultaneous production of reaction products. Possible solutions are:
- Very high pump speeds (overall very low concentration of reaction products)
- Dilution with inert gases (He, Ar)
- Change of the process properties such that the limiting step is not the reactant supply for instance by adding passivating gases.
- Find a way to favor reactive species consumption or recombination on the chamber walls
- Plasma pulsing to allow reaction products to be removed.

Microloading is caused by a localized depletion of the reactive species or accumulation of reaction by-products as a result of the local pattern density on the wafer (slide 3). Processes with strong macroloading typically also show strong microloading unless the mean free path of the species is much larger than the wafer diameter (which is not the case for normal operating pressures between 1 and 100 mTorr).

ARDE is caused by the effect of the wafer topography on the etch rate of a certain feature. Possible mechanisms have been described on a review paper by Gottscho at el. (JVST 10 (1992) 2133). These mechanisms include Knudsen transport of neutrals, ion shadowing, neutral shadowing, differential charging of insulating microstructures, charging of a polymer sidewall and the interaction of etch and deposition (slide 4).

ARDE has been shown to be dependent on the composition of the oxide for a SAC (selfaligned contact) etch process (slide 5).

SAC etch is a very polymerizing process and the question arises as to how ARDE depends on the interaction between deposition and etch (slide 6). From the experimental data it is clear, that polymerizing chemistries show a different ARDE than pure etching chemistries. In certain cases, heavily polymerizing processes show reverse ARDE (SAC and Al interconnect etch, for instance). To understand the effect of the polymer formation on ARDE, one has to consider the relative importance of etch and deposition and their transport to the etch front within the high aspect ratio microstructure.

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Knudsen Transport of Neutral Species

RIE lag or Aspect Ratio Dependent Etching (ARDE) is particularly important for high aspect ratio etching. One of the elementary mechanisms that can contribute to ARDE is the transport mechanism of the neutrals. Plasma etching or reactive ion etching relies on the presence of reactive neutrals and ions at the etch front. For very high aspect ratio features, the neutral flux gets attenuated. Coburn and Winters showed that this reduction of the neutral flux towards the bottom of the feature can be described by the Knudsen transport model used to describe vacuum systems. In this model, neutrals are lost either on the feature sidewall as described by the transmission probability or get reflected from the etching surface as described by the reaction probability. The remaining species contribute to the etching process (slide 1).

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Charging Effects

Charging effects during plasma etching of high aspect ratio structures can cause gate oxide degradation during gate etching and profile deformation issues such as notching or bowing. Charging effects become important for aspect ratios higher than 2:1. The origin of this phenomenon is due to the difference in directionality between ions and electrons when they cross the plasma sheath and interact with three dimensional structures (slide 1).

At low and medium frequencies (< 10 MHz), the ions enter the plasma sheath at different phases of the RF cycle resulting in a bi-modal ion energy distribution. For higher frequencies, the energy distribution exhibits only one peak since the period of the RF signal is much smaller than the time it takes for the ion to travel through the sheath resulting in the ion experiencing just an average field. Because of the acceleration in the sheath, the angular distribution is very directional for ions.

Electrons can respond to the instantaneous electric field, they enter the sheath with a Maxwellian energy distribution in speed but very isotropic directionality. The difference in directionality between ions and electrons leads to charging effects which may strongly impact plasma processes (slide 2).

The following discussion is adapted from Hwang and Giapis, JVST B15, 70, (1997). For featureless surfaces, ion and electron fluxes onto large open areas are equal. Any vertical surface on the wafer (feature sidewall) screens a part of the electron flux: the net flux of electrons arriving on the surface decreases. In contrast, the ion flux is not impacted. If the surface at the bottom is an insulator, it charges positively, possibly leading to a partial deviation of the ion flux. If the mask is an insulator, it will charge negatively. For two adjacent sidewalls are present (space between two lines or trenches), the shadowing effect becomes even more pronounced. The insulator between the lines will be charged even more (slide 3).

Simulations by Hwang and Giapis show that it takes about 1000 RF cycles for the ion and electron fluxes to reach a steady state. This leads to a strongly asymmetric potential distribution. A very strong peak potential develops inside the structure close to the last polysilicon line. The dramatic re-distribution of potential occurs leads to the conditions necessary for an ion trajectory deflection and ion acceleration towards the silicon sidewalls (slide 4).

In the steady state etching regime, 15 eV ions can get repelled away from the outer sidewall. The large positive potential at the trench bottom can slow down energetic ions so that they can be deflected and accelerated towards the lower part of the poly silicon sidewall. Increasing the ion energy to 30 eV reduces these effects (slide 5).

The very strong peak potential that develops close to the edge of the structure induces a ion trajectory distortion. Close to the edge of polysilicon, ions never reach SiO2 at the bottom. They get deflected by the high potential at the bottom that develops on the SiO2 surface and reach the polysilicon sidewalls. There, the ions can generate some etching if their energy is high enough to punch through the passivation layer (slide 6).

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Temperature Effects in Plasma Etching

The wafer surface temperature depends primarily on the chuck temperature, the ion density and ion energy and the exothermicity of the etching reaction. Surface temperature influences etching processes (slide 1):
- The Reaction probabilities of incident species depends on substrate temperature.
- The vapor pressure of etch products is temperature dependent.
- The re-deposition of reaction products on feature surfaces depends on temperature.

Tight control of the wafer surface temperature is an engineering challenges caused by sudden changes in the plasma condition during the transition between process steps. In addition, the true substrate temperature is difficult to monitor.

Slide 2 summarizes the findings on th selectivities and profile control for silicon etching in a SF6 plasma by S. Tachi et al. (Appl. Phys. Lett. 52 (1988) 617):
-At very low temperature, the silicon etch rate in SF6 based plasmas is not impacted
- SiO2 and photoresist etch rates decrease strongly for decreasing temperatures
- Spontaneous etching reaction between fluorine atomes and silicon are frozen for temperatures below -90°C (no under cut below an SiO2 hard mask).

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Silicon Etching Mechanisms with HBr and Cl2

The effects of exposing a single crystalline silicon surface to a halogen plasma can be studied with spectroscopic ellipsometry (SE). The measurements show that the surface layer is partially amorphized after plasma exposure. In addition, the existence of a halogen containing layer can be shown (slide 1).

Similar information can be obtained by XPS. The thickness of the amorphized layer is derived from the FHWM of the Si-Si peak (slide 2).

Slide 3 compares the thicknesses of the brominated top layer as measured by SE and XPS. Similarity between etch rate and halogen coverage suggests that the etch rate is limited by the ability of halogenated products at the surface to form volatile species. Halogen coverage can be limited by: thermal flux of neutrals, ion flux, steric hindrance. At etch rate saturation (20 As-1), the silicon atom removal rate is 1016 cm-2 s-1, thermal flux of HBr at 2 mTorr is higher than 1017 cm-2 s-1.

From the studies, the following conclusions can be drawn (slide 4):
- XPS and SE both indicate that the effective thickness of amorphized and halogenated layers are in the range 5-30 Å and increases with ion energy.
- The amorphization effect is almost identical for Cl2 and HBr plasmas.
- The halogenated layer is thicker for HBr.
- The etch rate saturates for HBr due to halogen coverage saturation.
- Halogen saturation is most likely attributed to steric hindrance by Br atoms.

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Plasma and Electrode Potentials

An RF plasma system can be represented by an equivalent circuit in the capacitive sheath approximation (slide 1). The cathode sheath and the anode (wall) sheath are represented by parallel ohmic and capacitive resistors as well as diode elements. The bulk plasma is an ohmic resistance. The RF signal generates a dc potential on the electrode which can be calculated knowing the RF voltage and the capacitances of the cathode and anode sheaths. For a symmetric reactor (areas of cathode and anode are approximately equal), the average plasma voltage is half of the sum of the RF and dc voltages.

Slide 2 illustrates the plasma and excitation electrode potentials for dc and capacitively coupled plasmas for different cathode to anode area ratios. Most plasma etch reactors are capacitively coupled and the anode (wall and reactor lid) have a much larger area compared to the cathode. For this type of reactor, the dc voltage is negative (which attracts positively charged ions to enhance the etch process) and the RF signal is positive with respect to ground only for a very short period of time. At this point in time, the plasma and RF voltages are equal. The plasma voltage is zero when the RF voltage reaches it's minimum.

Slide 3 shows the ion and electron currents to the powered electrode and the reactor walls for the capacitively coupled asymmetric reactor. A constant ion current is interrupted by a short burst of electron current when the peak voltage of the RF signal becomes positive with respect to ground. The time integrated ion and electron currents are equal maintaining the overall charge balance of the plasma.

The change of the electrode and wall potentials during the RF duty cycle is illustrated in slide 4 (compare to the lower right figure on slide 2).

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Capacitive and Inductive Coupling

Most low and medium plasma density reactors utilize capacitive coupling while high density plasmas can be generated by inductively coupled, electron cyclotron resonance (ECR) and some high frequency capacitively coupled reactors (slide 1). The capacitive coupling requires a high capacitance between the electrode and the plasma (large amplitude RF voltages). The inductive coupling requires a high inductance between a coil and the plasma (large RF currents). Capacitive coupling results in a high energy ion bombardment while the ion bombardment energy is much lower in inductively couples discharges. In a capacitive discharge, the periodic electron current flow to the electrode causes a modulation of the plasma potential. In an inductive discharge, the time varying current induces a time-varying magnetic field which induces a time varying electric field that can sustain the plasma.

An ideal capacitively coupled discharge is a vacuum chamber with two flat electrodes one of which connected to a rf power supply (typically the bottom electrode which supports the wafer (cathode) (slide 2). The ion density is weak, between 1E9 and 1E10 ion/cm-3. The discharge works in a pressure range between 10 and 100 mTorr. The self bias voltage (Vdc) can reach several hundreds of volts. Major drawback of this design is that it is impossible to control independently the ion density and ion energy.

Slide 3 illustrates the effect of the frequency of the RF signal on the ion energy distribution. Generally, the ion energy distribution function (IEDF) for very high frequencies is monoenergetic. For lower frequencies, the IEDF splits into two peaks with one low energy and one high energy component. The IEDF is ion mass dependent. The IEDF become distorted at higher pressures for which collisions can take place in the plasma sheath.

In addition to the cathode, one of the chamber surfaces, typically the lid, can be RF powered (slide 4). The frequency of the top electrode is usually higher than the frequency of the bias electrode. The higher the delta of the two frequencies, the better the decoupling. The high frequency contributes to the plasma density (anywhere between 1010 and 1012 ion/cm-3 depending on frequency and power) and the low frequency is used to tune the ion energy. The discharge works in a pressure range between below 10 and several 100 mTorr. The high frequency RF power can also be applied to the bottom electrode.

Slide 5 explains the differences between ohmic and stochastic heating in capacitively coupled reactors.

Generally, the plasma density increases when the excitation frequency is increased (slide 6). The exact correlation between plasma density and excitation frequency is however still subject of theoretical and experimental investigations. Nonlinearities have been reported repeatedly (see H. Goto et al., JVST A 10 (1992) 3048

In Magnetically Enhanced Reactive Ion Etching (MERIE), a magnetic field around the source suppresses electron neutralization on the chamber walls and increase the plasma density. The plasma generated is non-uniform due to the drift imposed by the magnetic field ( v x B where v is the electron velocity and B the local magnetic field). Electrons get accumulated on one side of the wafer leading to a strong plasma density and Vdc non-uniformity across the wafer (slide 7).

The plasma uniformity can be improved by introducing a magnetic field gradient close to the wafer or by using a rotating magnetic field. The self bias voltage (Vdc) across the wafer becomes therefore uniform allowing plasma induce damage to be strongly reduced (slide 8). In MERIE sources, ion density and energy cannot be independently controlled unless a second high frequency electrode is introduced.

The effect of the magnetic field in inductively coupled plasmas ICP) is described in slide 9. In ICP sources, a time varying current circulates in the coil and induces time varying magnetic and electric fields in the plasma which sustain the plasma.

Electron Cyclotron Resonance (ECR) plasmas are based on the coupling of an AC electric field, E, with a frequency which matches the frequency at which the electrons rotate in the constant magnetic field, the so called Larmor frequency (slide 10).

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MERIE and high density plasmas

Slide 1 shows a comparison between low / medium and high density plasmas. Magnetically Enhanced Reactive Ion Etching (MERIE) employs a medium density plasma. Alternative ways to generate low and medium density plasmas are capacitively coupled plasma sources with relatively low excitation frequencies and powers. High density plasma are usually generated by inductively coupled plasma (ICP) sources or sources based on the effect of electron cyclotron resonance (ECR). High density sources operate typically at lower pressures and are characterized by lower ion energies (slide 1).

Typical high density sources for plasma processing have a one order of magnitude higher radical and two order of magnitude higher ion density than medium density plasmas. These properties benefit chemical surface reactions and hence high density plasma sources are the sources of choice for silicon and metal etch (slide 2).

Slide 3 illustrates that for MERIE sources generate conditions under which the etch reaction requires the presence of neutral active species at the surface because the ion densities are too low. For high density plasmas, the theoretically explained by ion driven reactions only. This is most likely the reason why high density plasmas show very high resist erosion rates in oxide etching, the ion flux densities are too high (slide 3).

Slide 4 compares the sources with respect to the effects observed on the wafer. High density reactors were introduced primarily because ion density and energy are decoupled. This gives major advantages in gate etching with very thin gate oxides. The drawback of high density systems is the high density of ions, electrons and photons which can lead to enhanced resist erosion and bending, especially 193 nm resist. Dual frequency capacitive systems can operate in the low and medium density regime and are quasi decoupled. They are widely being used in dielectric etching. The degree of decoupling is higher the higher the source and the lower the bias frequency. High density etchers are used when the etch is very chemical (too high a radical density would make the etch hard to control) and when the passivation comes at least partially from the eroding resist, for instance metal etching.

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Influence of Mask Marterials in Silicon Gate Etching

The choice of the mask material for silicon gate etching depends on the process requirements. These materials can be grouped into carbon based materials (photoresists, bottom antireflective coatings (BARC) and carbon hardmasks) and silicon based dielectric masks (oxides, nitride, dielectric antireflective coatings (DARC)).

Slide 1 shows results of ellipsometry studies of the influence of the mask materials on the gate oxide etch rate. Under identical process conditions (HBr/Cl2/O2 standard chemistries), the gate oxide consumption is increased by a factor of 4 when going from a hardmask to a resist mask. This corroborates the common notion that resist masks tend to impact gate oxide selectivity negatively.

One possible explanation for the lower gate oxide selectivity is that carbon is liberated from the resist mask during the etch process and deposited on the gate oxide. Oxide tends to etch faster in the presence of carbon due to the formation of volatile carbon oxides. In-situ XPS studies of the gate oxide surface show that while Carbon is present on the gate oxide with the resist mask it is absent on the gate oxide with the SiO2 hardmask (slides 2 and 3).

The loss of gate oxide loss and the carbon concentration on the gate oxide surface both increase with the local resist coverage. When etching resist masked poly silicon gates, the poly-Si/SiO2 selectivity across the wafer is strongly affected by the local resist coverage (slide 4).

Besides concerns about the gate oxide selectivity, other reasons to use dielectric hardmasks in advanced gate etching include the dramatically reduced resist thickness / budget for advanced gate etching as well as mask charging (slide 5).

In-situ reflectometry measurements with a commercial predictive endpoint system provide additional evidence that the gate oxide erodes faster in the presence of photoresists on the wafer. In addition, the experiment reveals that the presence of silicon also lowers the gate oxide selectivity. This effect is smaller than for resist but measurable. A very uniform etch rate across the wafer is therefore mandatory to avoid local gate oxide pitting or punch through (slide 6).

Advanced poly-Si gate stack for high performance devices are frequently doped. Fluorine addition is frequently used to reduce the doping effect in advanced gate etching. CF4 addition is much more efficient than non-carbon containing gases like NF3. With respect to dielectric hardmasks, this has a double negative impact on mask selectivity: Both, fluorine and carbon increase the oxide or nitride etch rate and lower therefore the mask selectivity (slide 7).

The need for fluorocarbon addition drives the resurgence of resist schemes and the emergence of carbon and other alternative hardmasks (slide 8).

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Sidewall Passivation During Silicon Gate Etch

During silicon gate etching, anisotropy control is obtained by the formation of a passivation layer which forms on the gate sidewall and protects it from spontaneous etching reactions. The sidewall film thickness decreases along the gate sidewall showing that profile deformation is more likely to occur at the bottom of the gate profile. In the following, composition and thickness of the sidewall passivation layer will be investigated as a function as a function of the mask material, etch chemistry, and plasma operating conditions (slide 1).

XPS analyses performed on the gate sidewalls show that the passivation layer is a SiOxCly layer in a HBr/Cl2/O2 chemistry and a SiOxBry layer in a HBr/O2 chemistry (slide 2).

Slide 3 shows the influence of the mask material on the composition of the sidewall passivation layer. The overall differences are small, carbon from the resist mask seems not to play a major role in the passivation mechanism.

Comparing HBr/O2 and Cl2/O2 processes, the following observations were made: (1) The passivation film is a halogen rich oxide-like film, (2) The passivation film is thicker with HBr/O2 than with Cl2/O2, and (3) Chlorine in the gas mixture generates thin passivation layers (slide 4).

The passivation layer thickness is strongly dependent on the oxygen concentration in the gas phase (slide 5). Higher oxygen concentrations in the gas phase lead to thicker passivation layers.

XPS analysis after the silicon gate main etch and overetch show that during the overetch step, bromine is replaced by oxygen. Thus, the passivation layer is transformed into a more oxide like layer (slide 6).

Slide 7 summarizes the findings.

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The Selfclean Concept in Silicon Gate Etching

For the traditional HBr/Cl2/O2 silicon gate etch chemistry, high concentrations of etch products are present in the gas phase. These by-products can dissociate and form non volatile species. This leads to re-deposition of silicon oxyhalogenides on the feature sidewalls and in the presence of oxygen in the plasma to oxydation to form SiOx on the sidewalls. Direct line of sight re-deposition from the bottom of the features is also possible. The same mechanisms holds to explain the formation of SiOx on the chamber walls. The chamber wall will be covered with SiOx deposits (slide 1).

When CF4 is added, the formation of silicon oxyhalogenides is suppressed and silicon fluorides or oxyfluorides are formed. The SiOx based passivation film is replaced by a thin carbon rich layer (slide 2).

XPS studies reveal that the SiOxCly based passivation film is transformed in a CFxCly based passivation film when CF4 is added to the standard HBr/Cl2/O2 chemistry (slide 3).

In the steady state etching regime, a thin halogen rich fluorocarbon film is formed on the silicon surface at the bottom of the features (slide 4).

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RIE lag in poly-Si and silicide etching

RIE lag or Aspect Ratio Dependent Etching (ARDE) is particularly important for high aspect ratio gate stackes in dRAM and flash applications (slide 1). The RIE lag effect can be effectively impacted by the choice of a suitable gas additive. The underlaying mechanisms are not known. For general information on the origin of RIE lag, click here.

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Critical Dimension (CD) Control During Gate Etching

The term CD control describes requirements and methods to transfer a critical dimension of a mask (for instance the length of a transistor gate) into the final dimension of the etched feature (slide 1). During etching, a sidewall passivation layer is formed. This layer with it’s finite thickness constitutes a deviation from the original mask dimension. Critical dimension control is therefore sidewall passivation thickness control across die (dense and isolated lines etc.), across wafer, and wafer-to-wafer. The thickness of the passivation layer in turn is controlled by the balance between etch and deposition within each etching step and for all steps in combination. To achieve the highest possible pattern fidelity in advanced gate etch process, several hundred process parameters have to be selected and controlled in such a way that all features across a 300 mm wafer and among thousands of wafers do not deviate by more than 3 to 6 nm or 10 to 20 atoms.

Slide 2 shows the reaction mechanism and EELS analysis results for a poly-Si gate etch with HBr/Cl2/O2 chemistry. The EELS shows that the passivation layer on the mask and gate sidewalls is thicker than the CD deviation allowed across the entire wafer for sub 100 nm technology nodes. The passivation thickness is between 0 nm on the bottom and 9 nm on the top of the sidewall.

Slide 3 introduces the definition of CD bias and shows that it is determined by the sidewall passivation layer thickness. This passivsation layer is typically thicker in the isolated than in the dense area.

The definition of CD bias microloading is introduced in slide 4.

Anisotropic etching is a combination of isotropic etching and passivation deposition. Different etch processes will therefore show differences in the CD microloading depending on the relationship between deposition and etch (slide 5).

The etch proximity effect can be illustrated in a graph that shows CD bias microloading as a function of the CD bias. Different etch processes show dramatically different etch proximity effects depending on the underlaying etch mechanisms (slide 6).

Slide 7 shows the analysis of the etch proximity effect for a traditional HBr/Cl2/O2 poly-Si etch process in comparison to a CF4 added process (all other gases remain the same). When process parameter in main etch step are randomly varied, the CF4 added process shows clearly a better CD microloading behavior.

Slide 8 gives a tentative explanation for the difference in the etch proximity effect for the traditional poly-Si and the CF4 added process. The underlying root cause is that the passivation layer formation results from the competition between deposition and etch processes. If etch and deposition species originate both in the gas phase and show a similar aspect ratio dependence, the resulting passivation layer thickness should be less sensitive to the aspect ratio, i.e. open area.

Another example for etch proximity effects is given in slide 9 for a HBr/O2 based resist trim process. When CF4 is added to the chemistry, the dense lines show a larger CD bias (increased CD loss) compared to the Ar added process. This can be used in gate etching to compensate lithographic (optical) proximity effects during the resist trim step.

Slide 10 gives a tentative explanation for the proximity effect during resist trim.

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Dual Gate Etching: The Doping Effect

The etch rate and profiles for n- and p-doped as well as intrinsic poly-Si can differ from each other quite significantly depending on the plasma conditions and chemistry. Lee et al. explain these etch rate differences by Coulombic forces between the dopants and the halogen atom or molecule at the surface. Coulomb attraction between uncompensated donors (As or P) and chemisorbed halogens enhances etch rates in n-type silicon. Coulomb repulsion between uncompensated acceptors (B) and chemisorbed halogens inhibits etch rates in p-type silicon. This effect is the strongest in chlorine (slide 1).

Slide 2 shows the etch rates for n-doped and undoped poly-Si as well as the doped / undoped "selectivities" for HBr, Cl2, NF3 and CF4/O2 plasmas. All other reactor parameters such as pressure and power settings were kept constant. The experiment supports the finding that chlorine shows the strongest doping effect and the the chlorine in typical gate etch gas mixtures is the culprit for etch rate differences and profile distortions. Pure HBr exhibits the weakest doping effect followed by CF4/O2 and NF3.

Zhang et al. reported similar results for n-, p- and intrinsic poly-Si for CF4, HBr/Cl2 ans HBr/O2. Their findings show that HBr/O2 has the strongest doping effect for n-doped poly-Si. The effect for p-doped poly-Si is overall much smaller and similar for all three chemistries (slide 3).

Advanced gate structures are frequently pre-doped, i.e. the n- or p-dopants are introduced before the gate structures are etched. The doping levels rise as the devices are being scaled and can reach concentrations that lead to severe profile distortions. It was fund that the addition of CF4 to a traditional HBr / Cl2 / O2 poly-Si gate mainetch can reduce the doping effect. This is an additional benefit of the selfclean silicon etch chemistry. Slide 4 illustrates the effect of CF4 addition for various CF4 gas flows.

Slide 5 shows the doped/undoped selectivity as a function of pressure for 3 different poly-Si main etch processes: 1. HBr/Cl2/O2; 2. HBr/Cl2/O2/CF4 and 3. HBr/Cl2/O2/NF3. The etch rate difference increase at with higher pressure and have a maximum at around 20 mTorr (smallest Vdc). As expected, the doping effect for the Cf4 added process is small. Interestingly no effect was observed for NF3 addition. This points to carbon inhibitors rather than fluorine effect as mechanism for lowered doping sensitivity.

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Softlanding During Gate Etching

As gate dielectrics are being scaled down to a few atomic layers, the plasma conditions used to form the bulk of the poly-Si gate profile can not be used anymore to land on the gate dielectric. Predictive endpoint techniques have to be used to stop the main etch before the gate dielectric is being exposed. Slide 1 illustrates the need for an intermediate step which has better profile formation properties than the overetch and better selectivity than the main etch.

Slide 2 shows that the gate oxide shows pitting when the main etch touches the gate dielectric while no pitting is observed when a softlanding step is introduced. The softlanding step is therefore a very crucial step for advanced gate etching.

The process trends for a typical HBr / Cl2 / O2 softlanding step are different for gate structured patterned with photoresist or hardmask. Slide 3 and slide 4 show that the increase of the oxygen flow has opposite effects for both hardmask materials.

Two potential mechanisms for the oxygen effect on the softlanding profiles are given in slide 5 and 6. Slide 5 gives an explanation based on the assumption that an Increased ion flux leads to stronger mask charging and sidewall attack, i.e. foot removal. In the hardmask case, charging is not significant. A higher ion flux and the availability of oxygen species for SiOxBry formation would lead to more reaction products which can be deposited onto sidewall. This would lead to a more tapered profile and a profile foot.

An alternative mechanism is proposed in slide 6 based on the role of carbon in the passivation process. In the case of the resist mask, carbon released from the mask could participate in the passivation of the bottom sidewall. An increase of O2 flow either removes the source of carbon via formation of carbon oxides or potentially encapsulates mask with SiOxBry. In the case of a dielectric hardmask, there is no source of carbon to begin with. The enhanced availability of O for SiOxBry formation leads to more reaction products which are deposited onto sidewall. This leads to a more tapered profile and the formation of a profile foot.

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Gate Oxide Integrity

Silicon to oxide etch selectivity is not the only parameter describing the thickness of the gate oxide after a gate etch process. For gate oxides with a thickness of less than 4 nm, the removal of the top oxide layer during the overetch step is accompanied by other processes which will be described below. Slide 1 shows the result of an ellipsometry study of the thickness of such a very thin gate oxide during the exposure to an HBr based overetch process with a nominal selectivity of 80:1. While one would expect the gate oxide thickness to decrease, the experiment shows actually an increase of the gate oxide thickness.

A more detailed analysis with spectroscopic ellipsometry (SE) and XPS shows that for the given etch process, the remaining gate oxide thickness was at least 3.7 nm even when the original gate oxide was much thinner. From this it appears that during the exposure of very thin gate oxides to a HBr / O2 based overetch recipe, a re-oxidation of the gate oxide occurs. Effectively, the gate oxide is grown during plasma exposure (slide 2).

Spectroscopic ellipsometry shows that a perturbed layer as thick as 8 nm is formed when the gate oxide is exposed to a hydrogen plasma. Hydrogen ions, atoms or molecules penetrate the thin gate oxide and damage the bulk silicon underneath the gate oxide layer (slide 3).

FWHM analysis of the XPS signal of the surface confirms that the bulk silicon is amorphized by the diffusion of hydrogen species (slide 4).

The consequences of the gate oxide re-oxidation during the overetch step are illustrated by the TEM cross sections in slide 5. After the wetclean, the bulk silicon is recessed by a significant amount which depends on the plasma conditions.

A more detailed study on the plasma conditions which favor a minimum gate oxide recess has been published by Vitale and Smith (J. Vac. Sci. Technol. B21 (2003) 2205). Some of their findings are summarized in slide 6.

The influence of the electric field on the diffusion of hydrogen and oxygen through the gate oxide is discussed in slide 7. In the absence of bias power applied to the wafer, hydrogen and oxygen induced effects in crystal silicon below the gate oxide are not observed. The damage to the c-Si bulk below the gate oxide can be explained as follows. Hydrogen ions can be directly implanted through the gate oxide into the bulk silicon. Oxygen ions implanted in SiO2 generate defects in the gate oxide which may favor oxygen diffusion through SiO2 and in the silicon wafer.

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Thin Gate Oxide Behavior During Overetch Step

In this study, in-situ reflectometry was used to investigate the behavior of very thin gate oxides during exposure to HBr / O2 based plasmas which are typically being used in gate overetch recipes. A wavelength of 365 nm was chosen for the experiments (slide 1).

Slide 2 shows a typical signal of the light which was reflected from the poly-SI on gate oxide stack. It shows three distinct areas as seen in the corresponding SEM's of the surface morphology: a phase of poly-Si removal followed by gate oxide removal and gate oxide punch through.

A more detailed analysis shows the presence of a plateau after the clearance of the poly-Si which can be interpreted as a point in time when the gate oxide is exposed to the plasma but still intact. The length of this plateau represents the gate oxide life time. It was established in numerous experiments that this plateau is followed by a gradual change in the reflected ligth intensity where the signal rises or falls in alinear manner depending on the process conditions. It is assumed that this eriod in time corresponds to the co-existance of bulk silicon and oxide islands.After this transition, the signal flattens out because the surface is comprised of bulk silicon only. Slide 3 shows the signals for five different gate oxide thicknesses.

The analysis of the gate oxide life time and the transition time (gate oxide islands) as a function of the gate oxide thickness shows that the gate oxide life time decreases linearly with the gate oxide thickness. From the slope, a gate oxide etch rate of 113 A/min can be derived. The transition time does not significantly change with the gate oxide thickness because it is most likely related to the initial poly-Si roughness which was equal for all five samples (slide 4).

In another experiment, test chips were placed on carrier wafers which different areas of exposed silicon to simulate different loadig conditions. Slide 5 illustrates that the gate oxide life time is also a functiion of the silicon loading.

Slide 6 illustrates, that the gate oxide life time is dramatically reduced for conditions that are characterized by larger ion fluxes. The gate oxide life time is dropping faster than 1/W for an increasing source power and the silicon etch rate increase proportionally with the source power. This means that the selectivity to the gate oxide is reduced at higher source powers. The surprising result is that this effect is not compensated by the reduced ion energy.

It is known, that plasma oxidation can occur for thin gate oxides (< 50 Å). This would explain that good gate oxide selectivities can be achieved for higher ion energies since positively charged oxygen ions can pepentrate the gate oxide (slide 7).

TEM cross section reveal that the surface oxidation of the gate oxide / silicon interface by the presence of gate oxid"bending" or "recessing". This effect has to be minimized for advanced transistor devices in order to avoid large channel resistances (slide 8).

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Design of a Notched Gate Process

Gate notching is one technique to increase transistor speed by reducing the gate length and the source drain overlay capacitance. The challenges for this technology are repeatability and measurability as well as the difficulties associated with the spacer and implant integration (slide 1).

In the traditional silicon gate etch approach, the profile is formed with a sidewall passivation layer extending over the entire height of the profile. For the formation of a notched gate, the passivating silicon etch step is stopped at a desired height (notch height). This can be accomplished for instance with predictive endpoint. The bottom of the profile is etch with a fluorine containing etch chemistry which prevents to a large extend the formation of a protective sidewall layer. An HBr, Cl2, O2 and N2 containing overetch or notch step is introduced to etch laterally into the profile to form the desired notch. The notch depth and hence the gate length depends on the etch time which makes gate length control very dependent on the reactor condition (slide 2).

Slide 3 illustrates that germanium containing gate stacks are very well suited for the formation of notched gates. The notch height is controlled by the thickness of the germanium containing layer.

XPS spectra of the silicon gate sidewall show that traditional HBr / Cl2 / O2 based etch chemistries form dense and thick silicon oxide passivation layers, while Cl2/SF6 forms an anisotropic profile without any passivation layer thanks to a fast etching rate and a slow spontaneous etching rate of Cl species (slide 4).

The built up of silicon oxide containing layers on the reactor wall can severely impact the reproducibility of the lateral etch rate during the notching step (slide 5).

Slide 6 compares SF6 and CF4 containing etch processes. While Cl2/SF6 process chemistries form a passivation free sidewall layer, a mixture of Cl2 and CF4 is not suited for the notching due to the formation of a thin, probably carbon containing passivation layer.

Slide 7 shows the impact of aspect ratio dependent etching (ARDE) on the gate length of dense and isolated lines limits the application of the notched gate process to gate structures with a width larger than 100 nm. Below 100 nm, the critical dimensions of dense and isolated lines start to deviate significantly.

Slide 8 summarizes the key features of the notched gate process.

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