The wafer surface temperature depends primarily on the chuck temperature, the ion density and ion energy and the exothermicity of the etching reaction. Surface temperature influences etching processes (slide 1):
- The Reaction probabilities of incident species depends on substrate temperature.
- The vapor pressure of etch products is temperature dependent.
- The re-deposition of reaction products on feature surfaces depends on temperature.
Tight control of the wafer surface temperature is an engineering challenges caused by sudden changes in the plasma condition during the transition between process steps. In addition, the true substrate temperature is difficult to monitor.
Slide 2 summarizes the findings on th selectivities and profile control for silicon etching in a SF6 plasma by S. Tachi et al. (Appl. Phys. Lett. 52 (1988) 617):
-At very low temperature, the silicon etch rate in SF6 based plasmas is not impacted
- SiO2 and photoresist etch rates decrease strongly for decreasing temperatures
- Spontaneous etching reaction between fluorine atomes and silicon are frozen for temperatures below -90°C (no under cut below an SiO2 hard mask).
More plasma etch fundamentals …
Showing posts with label gate oxide selectivity. Show all posts
Showing posts with label gate oxide selectivity. Show all posts
Saturday, February 3, 2007
Influence of Mask Marterials in Silicon Gate Etching
The choice of the mask material for silicon gate etching depends on the process requirements. These materials can be grouped into carbon based materials (photoresists, bottom antireflective coatings (BARC) and carbon hardmasks) and silicon based dielectric masks (oxides, nitride, dielectric antireflective coatings (DARC)).
Slide 1 shows results of ellipsometry studies of the influence of the mask materials on the gate oxide etch rate. Under identical process conditions (HBr/Cl2/O2 standard chemistries), the gate oxide consumption is increased by a factor of 4 when going from a hardmask to a resist mask. This corroborates the common notion that resist masks tend to impact gate oxide selectivity negatively.
One possible explanation for the lower gate oxide selectivity is that carbon is liberated from the resist mask during the etch process and deposited on the gate oxide. Oxide tends to etch faster in the presence of carbon due to the formation of volatile carbon oxides. In-situ XPS studies of the gate oxide surface show that while Carbon is present on the gate oxide with the resist mask it is absent on the gate oxide with the SiO2 hardmask (slides 2 and 3).
The loss of gate oxide loss and the carbon concentration on the gate oxide surface both increase with the local resist coverage. When etching resist masked poly silicon gates, the poly-Si/SiO2 selectivity across the wafer is strongly affected by the local resist coverage (slide 4).
Besides concerns about the gate oxide selectivity, other reasons to use dielectric hardmasks in advanced gate etching include the dramatically reduced resist thickness / budget for advanced gate etching as well as mask charging (slide 5).
In-situ reflectometry measurements with a commercial predictive endpoint system provide additional evidence that the gate oxide erodes faster in the presence of photoresists on the wafer. In addition, the experiment reveals that the presence of silicon also lowers the gate oxide selectivity. This effect is smaller than for resist but measurable. A very uniform etch rate across the wafer is therefore mandatory to avoid local gate oxide pitting or punch through (slide 6).
Advanced poly-Si gate stack for high performance devices are frequently doped. Fluorine addition is frequently used to reduce the doping effect in advanced gate etching. CF4 addition is much more efficient than non-carbon containing gases like NF3. With respect to dielectric hardmasks, this has a double negative impact on mask selectivity: Both, fluorine and carbon increase the oxide or nitride etch rate and lower therefore the mask selectivity (slide 7).
The need for fluorocarbon addition drives the resurgence of resist schemes and the emergence of carbon and other alternative hardmasks (slide 8).
More plasma etch applications …
Slide 1 shows results of ellipsometry studies of the influence of the mask materials on the gate oxide etch rate. Under identical process conditions (HBr/Cl2/O2 standard chemistries), the gate oxide consumption is increased by a factor of 4 when going from a hardmask to a resist mask. This corroborates the common notion that resist masks tend to impact gate oxide selectivity negatively.
One possible explanation for the lower gate oxide selectivity is that carbon is liberated from the resist mask during the etch process and deposited on the gate oxide. Oxide tends to etch faster in the presence of carbon due to the formation of volatile carbon oxides. In-situ XPS studies of the gate oxide surface show that while Carbon is present on the gate oxide with the resist mask it is absent on the gate oxide with the SiO2 hardmask (slides 2 and 3).
The loss of gate oxide loss and the carbon concentration on the gate oxide surface both increase with the local resist coverage. When etching resist masked poly silicon gates, the poly-Si/SiO2 selectivity across the wafer is strongly affected by the local resist coverage (slide 4).
Besides concerns about the gate oxide selectivity, other reasons to use dielectric hardmasks in advanced gate etching include the dramatically reduced resist thickness / budget for advanced gate etching as well as mask charging (slide 5).
In-situ reflectometry measurements with a commercial predictive endpoint system provide additional evidence that the gate oxide erodes faster in the presence of photoresists on the wafer. In addition, the experiment reveals that the presence of silicon also lowers the gate oxide selectivity. This effect is smaller than for resist but measurable. A very uniform etch rate across the wafer is therefore mandatory to avoid local gate oxide pitting or punch through (slide 6).
Advanced poly-Si gate stack for high performance devices are frequently doped. Fluorine addition is frequently used to reduce the doping effect in advanced gate etching. CF4 addition is much more efficient than non-carbon containing gases like NF3. With respect to dielectric hardmasks, this has a double negative impact on mask selectivity: Both, fluorine and carbon increase the oxide or nitride etch rate and lower therefore the mask selectivity (slide 7).
The need for fluorocarbon addition drives the resurgence of resist schemes and the emergence of carbon and other alternative hardmasks (slide 8).
More plasma etch applications …
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